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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-04 22:23:50 -1000 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-05 10:07:41 -1000 |
| commit | bc16208aa51834aa9968af44678bedd5cdeb9d35 (patch) | |
| tree | c2127634b6efe9b117c339594b9bb53f8c3e0276 /riscv/insns/sfence_inval_ir.h | |
| parent | 263af1d153cd7cb684633a4ad631dc45b60464cf (diff) | |
| download | riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.zip riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.tar.gz riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.tar.bz2 | |
SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213
Diffstat (limited to 'riscv/insns/sfence_inval_ir.h')
| -rw-r--r-- | riscv/insns/sfence_inval_ir.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/sfence_inval_ir.h b/riscv/insns/sfence_inval_ir.h index f566d63..6f76a3f 100644 --- a/riscv/insns/sfence_inval_ir.h +++ b/riscv/insns/sfence_inval_ir.h @@ -1,3 +1,4 @@ require_extension('S'); require_extension(EXT_SVINVAL); require_impl(IMPL_MMU); +require_privilege_hs_qualified(PRV_S); |