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authorAndrew Waterman <andrew@sifive.com>2020-06-08 14:12:36 -0700
committerAndrew Waterman <andrew@sifive.com>2020-06-08 14:12:36 -0700
commit090a083f0d6499b830622bb10d4486afa1f2b448 (patch)
tree72ab1f980281027656a2f2b96e85c89021f7788c /riscv/insns/sc_w.h
parent33a6eb57564c257037780ddd2691ca621c44a55b (diff)
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Fix priority of misaligned exceptions for store-conditional
Previously, we unintentionally prioritized access faults and page faults. Resolves #431
Diffstat (limited to 'riscv/insns/sc_w.h')
-rw-r--r--riscv/insns/sc_w.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index fe4fcdc..e430dcb 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,7 +1,10 @@
require_extension('A');
-bool have_reservation = MMU.check_load_reservation(RS1);
-MMU.amo_uint32(RS1, [&](uint32_t lhs) { return have_reservation ? RS2 : lhs; });
+bool have_reservation = MMU.check_load_reservation(RS1, 4);
+
+if (have_reservation)
+ MMU.store_uint32(RS1, RS2);
+
MMU.yield_load_reservation();
WRITE_RD(!have_reservation);