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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-11 14:48:11 +0200 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-10-22 17:00:11 -0700 |
| commit | 70d7081acb5be54ea7fa4c3f9ef9a6134a43519e (patch) | |
| tree | 6bf1c33283d13b4b197047f225d45cd253ceaccf /riscv/insns/rolw.h | |
| parent | f1c24eff543e6f41980993f41ae1ab5ab80a7340 (diff) | |
| download | riscv-isa-sim-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.zip riscv-isa-sim-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.tar.gz riscv-isa-sim-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.tar.bz2 | |
[riscv-bitmanip] Add bitmanip instructions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'riscv/insns/rolw.h')
| -rw-r--r-- | riscv/insns/rolw.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/insns/rolw.h b/riscv/insns/rolw.h new file mode 100644 index 0000000..6d66a50 --- /dev/null +++ b/riscv/insns/rolw.h @@ -0,0 +1,5 @@ +require_rv64; +require_extension('B'); +int shamt = RS2 & 31; +int rshamt = -shamt & 31; +WRITE_RD(sext32((RS1 << shamt) | (zext32(RS1) >> rshamt))); |