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| author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:34:02 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-30 11:33:03 +0800 |
| commit | e205ca655c12df1ae0f6f3105bc8a671b049f161 (patch) | |
| tree | 5994a35a1995f8dd55aefdf5db2ae00bb61f44f5 /riscv/insns/ori.h | |
| parent | 456913b2c97d55993103594991a7ac73453465f8 (diff) | |
| download | riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.zip riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.tar.gz riscv-isa-sim-e205ca655c12df1ae0f6f3105bc8a671b049f161.tar.bz2 | |
add instructions function for cmo
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
Diffstat (limited to 'riscv/insns/ori.h')
| -rw-r--r-- | riscv/insns/ori.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h index 6403c39..3aba1cb 100644 --- a/riscv/insns/ori.h +++ b/riscv/insns/ori.h @@ -1 +1,2 @@ +// prefetch.i/r/w hint when rd = 0 and i_imm[4:0] = 0/1/3 WRITE_RD(insn.i_imm() | RS1); |