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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:24:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:34:25 -0700 |
| commit | d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (patch) | |
| tree | cbcbf16cef050f44dd8a7d0992878ee142e6f0b0 /riscv/insns/lwu.h | |
| parent | 8d40946475d73ce2627549b1857991d70cb1186b (diff) | |
| download | riscv-isa-sim-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.zip riscv-isa-sim-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.gz riscv-isa-sim-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.bz2 | |
Template-ize loads
Diffstat (limited to 'riscv/insns/lwu.h')
| -rw-r--r-- | riscv/insns/lwu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index dcc4d75..cbc7e2a 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm())); +WRITE_RD(MMU.load<uint32_t>(RS1 + insn.i_imm())); |