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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-18 18:28:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-18 18:28:05 -0700 |
| commit | 01c01cc36f006cfb03cd6d1c5a68f926b93f7787 (patch) | |
| tree | 1bc5333057ff935073a595834092e4dd0936e34d /riscv/insns/ld.h | |
| download | riscv-isa-sim-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.zip riscv-isa-sim-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.tar.gz riscv-isa-sim-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.tar.bz2 | |
Reorganized directory structure
Moved cross-compiler to /xcc/ rather than /
Added ISA sim in /sim/
Added Proxy Kernel in /pk/ (to be cleaned up)
Added opcode map to /opcodes/ (ditto)
Added documentation to /doc/
Diffstat (limited to 'riscv/insns/ld.h')
| -rw-r--r-- | riscv/insns/ld.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h new file mode 100644 index 0000000..45bbcc2 --- /dev/null +++ b/riscv/insns/ld.h @@ -0,0 +1,2 @@ +require64; +RT = mmu.load_int64(RS+SIMM); |