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| author | Andrew Waterman <andrew@sifive.com> | 2020-09-24 17:05:15 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-09-24 17:05:43 -0700 |
| commit | 77024fa1d1303b1274ff25de335ef8e67092b201 (patch) | |
| tree | a8951c0eb33db7b27c253ae98483c13faa72307e /riscv/insns/hsv_d.h | |
| parent | 43003ea3ed9d2c1a1c060416da91ccf5b044c55c (diff) | |
| download | riscv-isa-sim-77024fa1d1303b1274ff25de335ef8e67092b201.zip riscv-isa-sim-77024fa1d1303b1274ff25de335ef8e67092b201.tar.gz riscv-isa-sim-77024fa1d1303b1274ff25de335ef8e67092b201.tar.bz2 | |
Fix priority of virtual vs. illegal instruction exceptions for HLV/HSV
Resolves #551
Diffstat (limited to 'riscv/insns/hsv_d.h')
| -rw-r--r-- | riscv/insns/hsv_d.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/hsv_d.h b/riscv/insns/hsv_d.h index 2952c65..14c6d5d 100644 --- a/riscv/insns/hsv_d.h +++ b/riscv/insns/hsv_d.h @@ -1,5 +1,5 @@ require_extension('H'); require_rv64; -require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_U : PRV_S); require_novirt(); +require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_U : PRV_S); MMU.guest_store_uint64(RS1, RS2); |