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| author | Anup Patel <anup.patel@wdc.com> | 2020-06-19 17:56:05 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-07-09 23:04:18 +0530 |
| commit | 564ed97f618321b8499a3e8837c36f622ee8a893 (patch) | |
| tree | 81754eab18ac55c64f7c2b3017c451d99bb9d457 /riscv/insns/hsv_d.h | |
| parent | b75aff9e5d132a16d9326bc0b3bbc724ae3c753c (diff) | |
| download | riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.zip riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.tar.gz riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.tar.bz2 | |
Implement new instructions of hypervisor extension
We add new HFENCE, HLV, and HSV instructions for HS-mode which
are defined as part of the RISC-V hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/insns/hsv_d.h')
| -rw-r--r-- | riscv/insns/hsv_d.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/insns/hsv_d.h b/riscv/insns/hsv_d.h new file mode 100644 index 0000000..6d41fb8 --- /dev/null +++ b/riscv/insns/hsv_d.h @@ -0,0 +1,5 @@ +require_extension('H'); +require_rv64; +require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U); +require_novirt(); +MMU.guest_store_uint64(RS1, RS2); |