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author | Andrew Waterman <andrew@sifive.com> | 2020-09-20 18:58:02 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-09-20 18:58:02 -0700 |
commit | fbb5a7620ffd2d6f7583148881e2c9fc501a4614 (patch) | |
tree | 626136c9828623f1f32ecf42c91d2cab93838959 /riscv/insns/hlvx_wu.h | |
parent | d6ac560a1cf60e1364c26ec5fb673b38993caaa3 (diff) | |
download | riscv-isa-sim-fbb5a7620ffd2d6f7583148881e2c9fc501a4614.zip riscv-isa-sim-fbb5a7620ffd2d6f7583148881e2c9fc501a4614.tar.gz riscv-isa-sim-fbb5a7620ffd2d6f7583148881e2c9fc501a4614.tar.bz2 |
Fix polarity of hstatus.HU field
Diffstat (limited to 'riscv/insns/hlvx_wu.h')
-rw-r--r-- | riscv/insns/hlvx_wu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/hlvx_wu.h b/riscv/insns/hlvx_wu.h index 515b46e..cb4477a 100644 --- a/riscv/insns/hlvx_wu.h +++ b/riscv/insns/hlvx_wu.h @@ -1,4 +1,4 @@ require_extension('H'); -require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U); +require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_U : PRV_S); require_novirt(); WRITE_RD(MMU.guest_load_x_uint32(RS1)); |