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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 17:36:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:12:25 -0700 |
| commit | 5cdb39484c531814a6640c1ec976a61d2ad21333 (patch) | |
| tree | 1a48557d14789a25bc7e17f07112faecdc4bbea0 /riscv/insns/hlv_h.h | |
| parent | a09b88d4abb8fe3015c3921c7468e78b7f09da15 (diff) | |
| download | riscv-isa-sim-5cdb39484c531814a6640c1ec976a61d2ad21333.zip riscv-isa-sim-5cdb39484c531814a6640c1ec976a61d2ad21333.tar.gz riscv-isa-sim-5cdb39484c531814a6640c1ec976a61d2ad21333.tar.bz2 | |
Template-ize hypervisor loads and stores
Diffstat (limited to 'riscv/insns/hlv_h.h')
| -rw-r--r-- | riscv/insns/hlv_h.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/hlv_h.h b/riscv/insns/hlv_h.h index 4cb07e9..f2e14c4 100644 --- a/riscv/insns/hlv_h.h +++ b/riscv/insns/hlv_h.h @@ -1,4 +1,4 @@ require_extension('H'); require_novirt(); require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); -WRITE_RD(MMU.guest_load_int16(RS1)); +WRITE_RD(MMU.guest_load<int16_t>(RS1)); |