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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-24 20:34:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-09-28 15:56:47 -0700 |
| commit | 85c40db208db3e26f507dc6a74a5dc540b504b5c (patch) | |
| tree | 88ddd7440be666a4305a55e4ca1130ae7636a4f6 /riscv/insns/fmadd_q.h | |
| parent | bd85811c35ea38180d27440507fc222d585ef780 (diff) | |
| download | riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.zip riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.gz riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.bz2 | |
Implement Q extension
Diffstat (limited to 'riscv/insns/fmadd_q.h')
| -rw-r--r-- | riscv/insns/fmadd_q.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/insns/fmadd_q.h b/riscv/insns/fmadd_q.h new file mode 100644 index 0000000..882dfc1 --- /dev/null +++ b/riscv/insns/fmadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128(FRS3))); +set_fp_exceptions; |