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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-17 20:38:34 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-04-03 16:55:14 -0700 |
| commit | 09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa (patch) | |
| tree | 36b92616ad46d34ab23606a883f6e835a11f0f2d /riscv/insns/fli_q.h | |
| parent | f002b931d076af91c35dad05dd54580112b4a9d6 (diff) | |
| download | riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.zip riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.gz riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.bz2 | |
Implement Zfa.
This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
Diffstat (limited to 'riscv/insns/fli_q.h')
| -rw-r--r-- | riscv/insns/fli_q.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/riscv/insns/fli_q.h b/riscv/insns/fli_q.h new file mode 100644 index 0000000..7ba569b --- /dev/null +++ b/riscv/insns/fli_q.h @@ -0,0 +1,46 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +{ + const uint64_t bits[32] = { + [0b00000] = 0xBFFF000000000000ull, /* -1.0 */ + [0b00001] = 0x0001000000000000ull, /* minimum positive normal */ + [0b00010] = 0x3FEF000000000000ull, /* 1.0 * 2^-16 */ + [0b00011] = 0x3FF0000000000000ull, /* 1.0 * 2^-15 */ + [0b00100] = 0x3FF7000000000000ull, /* 1.0 * 2^-8 */ + [0b00101] = 0x3FF8000000000000ull, /* 1.0 * 2^-7 */ + [0b00110] = 0x3FFB000000000000ull, /* 1.0 * 2^-4 */ + [0b00111] = 0x3FF9000000000000ull, /* 1.0 * 2^-3 */ + [0b01000] = 0x3FFD000000000000ull, /* 0.25 */ + [0b01001] = 0x3FFD400000000000ull, /* 0.3125 */ + [0b01010] = 0x3FFD800000000000ull, /* 0.375 */ + [0b01011] = 0x3FFDC00000000000ull, /* 0.4375 */ + [0b01100] = 0x3FFE000000000000ull, /* 0.5 */ + [0b01101] = 0x3FFE400000000000ull, /* 0.625 */ + [0b01110] = 0x3FFE800000000000ull, /* 0.75 */ + [0b01111] = 0x3FFEC00000000000ull, /* 0.875 */ + [0b10000] = 0x3FFF000000000000ull, /* 1.0 */ + [0b10001] = 0x3FFF400000000000ull, /* 1.25 */ + [0b10010] = 0x3FFFC00000000000ull, /* 1.5 */ + [0b10011] = 0x4000000000000000ull, /* 1.75 */ + [0b10100] = 0x4000400000000000ull, /* 2.0 */ + [0b10101] = 0x4000800000000000ull, /* 2.5 */ + [0b10110] = 0x4001000000000000ull, /* 3 */ + [0b10111] = 0x4002000000000000ull, /* 4 */ + [0b11000] = 0x4003000000000000ull, /* 8 */ + [0b11001] = 0x400D000000000000ull, /* 16 */ + [0b11010] = 0x4006000000000000ull, /* 2^7 */ + [0b11011] = 0x4007000000000000ull, /* 2^8 */ + [0b11100] = 0x400E000000000000ull, /* 2^15 */ + [0b11101] = 0x400F000000000000ull, /* 2^16 */ + [0b11110] = 0x7FFF000000000000ull, /* +inf */ + [0b11111] = defaultNaNF128UI64 + }; + + static_assert(defaultNaNF128UI0 == 0, "LSBs of quad-precision NaN must be zero"); + + ui128_f128 ui; + ui.ui.v64 = bits[insn.rs1()]; + ui.ui.v0 = 0; + WRITE_FRD(f128(ui.f)); +} |