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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-17 20:38:34 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-04-03 16:55:14 -0700 |
| commit | 09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa (patch) | |
| tree | 36b92616ad46d34ab23606a883f6e835a11f0f2d /riscv/insns/fleq_q.h | |
| parent | f002b931d076af91c35dad05dd54580112b4a9d6 (diff) | |
| download | riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.zip riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.gz riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.bz2 | |
Implement Zfa.
This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
Diffstat (limited to 'riscv/insns/fleq_q.h')
| -rw-r--r-- | riscv/insns/fleq_q.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/insns/fleq_q.h b/riscv/insns/fleq_q.h new file mode 100644 index 0000000..8533d11 --- /dev/null +++ b/riscv/insns/fleq_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f128_le_quiet(f128(FRS1), f128(FRS2))); |