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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/fcvt_s_wu.h | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | riscv-isa-sim-plic_uart_v1.zip riscv-isa-sim-plic_uart_v1.tar.gz riscv-isa-sim-plic_uart_v1.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/fcvt_s_wu.h')
-rw-r--r-- | riscv/insns/fcvt_s_wu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h index c1394c3..ec90fad 100644 --- a/riscv/insns/fcvt_s_wu.h +++ b/riscv/insns/fcvt_s_wu.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f32((uint32_t)RS1)); +WRITE_FRD_F(ui32_to_f32((uint32_t)RS1)); set_fp_exceptions; |