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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/fcvt_h_d.h | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | riscv-isa-sim-plic_uart_v1.zip riscv-isa-sim-plic_uart_v1.tar.gz riscv-isa-sim-plic_uart_v1.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/fcvt_h_d.h')
| -rw-r--r-- | riscv/insns/fcvt_h_d.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h index e9987b7..e06b1a5 100644 --- a/riscv/insns/fcvt_h_d.h +++ b/riscv/insns/fcvt_h_d.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFHMIN); -require_extension('D'); +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_to_f16(f64(FRS1))); +WRITE_FRD_H(f64_to_f16(FRS1_D)); set_fp_exceptions; |