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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-12 20:27:10 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-12 20:27:10 -0700 |
| commit | 740f981cfd55604d46598144dccac26dd53f643c (patch) | |
| tree | 4b825dc642cb6eb9a060e54bf8d69288fbee4904 /riscv/insns/divw.h | |
| parent | c0ebf99d6bb3ef3cf252703b50b849bcbaa2ec59 (diff) | |
| download | riscv-isa-sim-740f981cfd55604d46598144dccac26dd53f643c.zip riscv-isa-sim-740f981cfd55604d46598144dccac26dd53f643c.tar.gz riscv-isa-sim-740f981cfd55604d46598144dccac26dd53f643c.tar.bz2 | |
[sim] renamed to riscv-isa-run
Diffstat (limited to 'riscv/insns/divw.h')
| -rw-r--r-- | riscv/insns/divw.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h deleted file mode 100644 index 51c3d80..0000000 --- a/riscv/insns/divw.h +++ /dev/null @@ -1,7 +0,0 @@ -require_xpr64; -if(RS2 == 0) - RD = UINT64_MAX; -else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) - RD = RS1; -else - RD = sext32(int32_t(RS1) / int32_t(RS2)); |