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author | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-16 19:44:52 -0700 |
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committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-16 19:44:52 -0700 |
commit | 95d58037b2fece5db3ca45a2eb8a1b22967f81f9 (patch) | |
tree | afd7e1fc46506005e3863b47be145a298fb42fdf /riscv/insns/divuw.h | |
parent | 6e2844c1b5d1b2c8bbc6b36a29726c19fd0c0593 (diff) | |
download | riscv-isa-sim-95d58037b2fece5db3ca45a2eb8a1b22967f81f9.zip riscv-isa-sim-95d58037b2fece5db3ca45a2eb8a1b22967f81f9.tar.gz riscv-isa-sim-95d58037b2fece5db3ca45a2eb8a1b22967f81f9.tar.bz2 |
[sim] removed undefined behavior for non-canonical inputs
Diffstat (limited to 'riscv/insns/divuw.h')
-rw-r--r-- | riscv/insns/divuw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h index 4d64be3..0ceb040 100644 --- a/riscv/insns/divuw.h +++ b/riscv/insns/divuw.h @@ -2,4 +2,4 @@ require_xpr64; if(RS2 == 0) RD = UINT64_MAX; else - RD = sext32(RS1 / RS2); + RD = sext32(zext32(RS1) / zext32(RS2)); |