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| author | Andrew Waterman <andrew@sifive.com> | 2020-09-20 18:53:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-09-20 18:53:27 -0700 |
| commit | d6ac560a1cf60e1364c26ec5fb673b38993caaa3 (patch) | |
| tree | ec0d96ee8e7c27dda5edcb7f59de5b05dfafc938 /riscv/insns/csrrw.h | |
| parent | 3e7cba464d9ce1a5ca5030b7e689d189874f8c75 (diff) | |
| download | riscv-isa-sim-d6ac560a1cf60e1364c26ec5fb673b38993caaa3.zip riscv-isa-sim-d6ac560a1cf60e1364c26ec5fb673b38993caaa3.tar.gz riscv-isa-sim-d6ac560a1cf60e1364c26ec5fb673b38993caaa3.tar.bz2 | |
Don't throw virtual instruction exceptions for unimplemented CSRs
Diffstat (limited to 'riscv/insns/csrrw.h')
| -rw-r--r-- | riscv/insns/csrrw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h index 94be3ad..cc0c28d 100644 --- a/riscv/insns/csrrw.h +++ b/riscv/insns/csrrw.h @@ -1,5 +1,5 @@ int csr = validate_csr(insn.csr(), true); -reg_t old = p->get_csr(csr, insn); +reg_t old = p->get_csr(csr, insn, true); p->set_csr(csr, RS1); WRITE_RD(sext_xlen(old)); serialize(); |