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author | Andy Wright <acwright@mit.edu> | 2016-05-21 16:39:21 -0400 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-05-21 13:39:21 -0700 |
commit | 8981e571623dba178d3aac147696772c8f9050bd (patch) | |
tree | 85117e7fcafc14eb305fd94678b5f57fe8dcba0f /riscv/insns/csrrci.h | |
parent | 07d2edff33bb0acf87305a6c54c0fcc5522c81e4 (diff) | |
download | riscv-isa-sim-8981e571623dba178d3aac147696772c8f9050bd.zip riscv-isa-sim-8981e571623dba178d3aac147696772c8f9050bd.tar.gz riscv-isa-sim-8981e571623dba178d3aac147696772c8f9050bd.tar.bz2 |
Some bugfixes for CSR reading and setting FS for fflags updates (#43)
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0
* Dirty fp state when setting new fp exceptions
* Set FS to dirty for all non-zero fflags writes.
Diffstat (limited to 'riscv/insns/csrrci.h')
-rw-r--r-- | riscv/insns/csrrci.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h index 993f2d8..986d601 100644 --- a/riscv/insns/csrrci.h +++ b/riscv/insns/csrrci.h @@ -1,4 +1,7 @@ -int csr = validate_csr(insn.csr(), true); +bool write = insn.rs1() != 0; +int csr = validate_csr(insn.csr(), write); reg_t old = p->get_csr(csr); -p->set_csr(csr, old & ~(reg_t)insn.rs1()); +if (write) { + p->set_csr(csr, old & ~(reg_t)insn.rs1()); +} WRITE_RD(sext_xlen(old)); |