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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-06 18:31:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-06 18:31:20 -0700 |
| commit | 686674dc15c1734940614c8f59419e9f94d51a52 (patch) | |
| tree | c0edd06e8b77b01e335f5f7f7bc098baeb62aac1 /riscv/insns/crc32_h.h | |
| parent | a718f061d71a316b7190469a53fd4834c0d41ae8 (diff) | |
| download | riscv-isa-sim-686674dc15c1734940614c8f59419e9f94d51a52.zip riscv-isa-sim-686674dc15c1734940614c8f59419e9f94d51a52.tar.gz riscv-isa-sim-686674dc15c1734940614c8f59419e9f94d51a52.tar.bz2 | |
Move bitmanip instructions outside Zba/Zbb/Zbc/Zbs into Xbitmanip
Diffstat (limited to 'riscv/insns/crc32_h.h')
| -rw-r--r-- | riscv/insns/crc32_h.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/crc32_h.h b/riscv/insns/crc32_h.h index 91bb253..73e7683 100644 --- a/riscv/insns/crc32_h.h +++ b/riscv/insns/crc32_h.h @@ -1,4 +1,4 @@ -require_extension('B'); +require_extension(EXT_XBITMANIP); reg_t x = zext_xlen(RS1); for (int i = 0; i < 16; i++) x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1)); |