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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:36:04 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:39:53 -0800 |
| commit | 1160ea7f1b1026884bef3b8ac2caf613c8e9a475 (patch) | |
| tree | a7ab9c0f38f3ab3360901159634555dc7c3cb799 /riscv/insns/cm_pop.h | |
| parent | b60d5766bf1cb3b3162c091cdc6a999f55d340e8 (diff) | |
| download | riscv-isa-sim-1160ea7f1b1026884bef3b8ac2caf613c8e9a475.zip riscv-isa-sim-1160ea7f1b1026884bef3b8ac2caf613c8e9a475.tar.gz riscv-isa-sim-1160ea7f1b1026884bef3b8ac2caf613c8e9a475.tar.bz2 | |
add support for zcmp
Diffstat (limited to 'riscv/insns/cm_pop.h')
| -rw-r--r-- | riscv/insns/cm_pop.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/riscv/insns/cm_pop.h b/riscv/insns/cm_pop.h new file mode 100644 index 0000000..0563bf5 --- /dev/null +++ b/riscv/insns/cm_pop.h @@ -0,0 +1,17 @@ +require_zcmp_pushpop; + +const auto new_sp = SP + insn.zcmp_stack_adjustment(xlen); +auto addr = new_sp; + +for (int i = Sn(11); i >= 0; i--) { + if (insn.zcmp_regmask() & (1 << i)) { + addr -= xlen / 8; + + if (xlen == 32) + WRITE_REG(i, MMU.load<int32_t>(addr)); + else + WRITE_REG(i, MMU.load<int64_t>(addr)); + } +} + +WRITE_REG(X_SP, new_sp); |