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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:27:12 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 15:37:52 -0800 |
| commit | b60d5766bf1cb3b3162c091cdc6a999f55d340e8 (patch) | |
| tree | e8afcf5577df9408a21f7bd818641d16f96d8959 /riscv/insns/c_not.h | |
| parent | 0adf9307eaef62402c4368d33e88bbb5e1211653 (diff) | |
| download | riscv-isa-sim-b60d5766bf1cb3b3162c091cdc6a999f55d340e8.zip riscv-isa-sim-b60d5766bf1cb3b3162c091cdc6a999f55d340e8.tar.gz riscv-isa-sim-b60d5766bf1cb3b3162c091cdc6a999f55d340e8.tar.bz2 | |
add support for zcb
Diffstat (limited to 'riscv/insns/c_not.h')
| -rw-r--r-- | riscv/insns/c_not.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/c_not.h b/riscv/insns/c_not.h new file mode 100644 index 0000000..26c1626 --- /dev/null +++ b/riscv/insns/c_not.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS1S(sext_xlen(~RVC_RS1S)); |