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| author | Tim Newsome <tim@sifive.com> | 2017-09-21 12:42:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-09-21 12:42:20 -0700 |
| commit | b86f2a51f522f020ad0d90f598f4c501f41da232 (patch) | |
| tree | 2c466d6f2c5a8a22f266d607f6e95b95f8dcc33a /riscv/insns/c_fsw.h | |
| parent | c471f5d84e2fc27e3eb4c2997635d3f2c83d7818 (diff) | |
| download | riscv-isa-sim-b86f2a51f522f020ad0d90f598f4c501f41da232.zip riscv-isa-sim-b86f2a51f522f020ad0d90f598f4c501f41da232.tar.gz riscv-isa-sim-b86f2a51f522f020ad0d90f598f4c501f41da232.tar.bz2 | |
Fix corner case in repeated execution (#127)
Specifically, don't print out the execution count if the same
instruction is executed by different harts.
Diffstat (limited to 'riscv/insns/c_fsw.h')
0 files changed, 0 insertions, 0 deletions