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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-08 17:12:32 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-08 17:12:32 -0800 |
| commit | c9af3ebbcc05fa901087085f8990824d578eb83c (patch) | |
| tree | 34eea4da5ceafd19013af60434abf9593798ca1f /riscv/insns/bset.h | |
| parent | c14c1ab21ea3dbd66ba5355b0a0cbaecdaed050e (diff) | |
| download | riscv-isa-sim-c9af3ebbcc05fa901087085f8990824d578eb83c.zip riscv-isa-sim-c9af3ebbcc05fa901087085f8990824d578eb83c.tar.gz riscv-isa-sim-c9af3ebbcc05fa901087085f8990824d578eb83c.tar.bz2 | |
Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft
Diffstat (limited to 'riscv/insns/bset.h')
| -rw-r--r-- | riscv/insns/bset.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/bset.h b/riscv/insns/bset.h new file mode 100644 index 0000000..0e3f0fc --- /dev/null +++ b/riscv/insns/bset.h @@ -0,0 +1,3 @@ +require_extension('B'); +int shamt = RS2 & (xlen-1); +WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); |