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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-21 00:26:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-21 00:26:51 -0800 |
| commit | c379868bd9b38e70e2f6ac757de80b27d416e2bf (patch) | |
| tree | 9ffaa3a89ec1552397b15f87f41e3483f85ccbef /riscv/execute.cc | |
| parent | edcf2d59b7019798f5c2ab303734883936c0b947 (diff) | |
| download | riscv-isa-sim-c379868bd9b38e70e2f6ac757de80b27d416e2bf.zip riscv-isa-sim-c379868bd9b38e70e2f6ac757de80b27d416e2bf.tar.gz riscv-isa-sim-c379868bd9b38e70e2f6ac757de80b27d416e2bf.tar.bz2 | |
Support histogram regardless of configure flag
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 08aeda0..b1f87e6 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -152,9 +152,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) inline void processor_t::update_histogram(reg_t UNUSED pc) { -#ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; -#endif } // These two functions are expected to be inlined by the compiler separately in |