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author | YenHaoChen <howard25336284@gmail.com> | 2022-11-16 11:49:44 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 07:44:04 +0800 |
commit | 8ffff21ac65199dfe56a95388f959e7ee7095561 (patch) | |
tree | 807d54ecedb38f8f2556d6323bf6730cb8020871 /riscv/execute.cc | |
parent | c87b2cbe33e998cde01e0c218dc6ab7f2251eec5 (diff) | |
download | riscv-isa-sim-8ffff21ac65199dfe56a95388f959e7ee7095561.zip riscv-isa-sim-8ffff21ac65199dfe56a95388f959e7ee7095561.tar.gz riscv-isa-sim-8ffff21ac65199dfe56a95388f959e7ee7095561.tar.bz2 |
triggers: add itrigger_t
add module_t::trap_taking_match and trigger_t::trap_taking_match for
checking itrigger after taking traps
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 6583a14..1426d2d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -301,7 +301,11 @@ void processor_t::step(size_t n) take_trap(t, pc); n = instret; - if (unlikely(state.single_step == state.STEP_STEPPED)) { + // Trigger action takes priority over single step + triggers::match_result_t match = TM.detect_trap_match(t); + if (match.fire) + take_trigger_action(match.action, 0, state.pc); + else if (unlikely(state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; enter_debug_mode(DCSR_CAUSE_STEP); } |