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author | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
commit | 0e83fe66fbf7b918602476bbaacfa6198a90d337 (patch) | |
tree | 93a72f8e0f093f1c872a0cacb2d822c166954bc0 /riscv/execute.cc | |
parent | 7a2ff14bff461f2c7adfbf407e11527f55d920db (diff) | |
download | riscv-isa-sim-rivosinc-etrigger_fix_exception_match.zip riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.gz riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.bz2 |
Call stash_privilege more selectivelyrivosinc-etrigger_fix_exception_match
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 0751476..69dbd7d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -14,12 +14,12 @@ static void commit_log_reset(processor_t* p) p->get_state()->log_mem_write.clear(); } -static void stash_privilege(processor_t* p) +void processor_t::stash_privilege() { - state_t* state = p->get_state(); + state_t* state = get_state(); state->last_inst_priv = state->prv; - state->last_inst_xlen = p->get_xlen(); - state->last_inst_flen = p->get_flen(); + state->last_inst_xlen = get_xlen(); + state->last_inst_flen = get_flen(); state->last_v = state->v; } @@ -161,7 +161,6 @@ inline void processor_t::update_histogram(reg_t pc) // These two functions are expected to be inlined by the compiler separately in // the processor_t::step() loop. The logged variant is used in the slow path static inline reg_t execute_insn_fast(processor_t* p, reg_t pc, insn_fetch_t fetch) { - stash_privilege(p); return fetch.func(p, fetch.insn, pc); } static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t fetch) @@ -169,7 +168,6 @@ static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t f if (p->get_log_commits_enabled()) { commit_log_reset(p); } - stash_privilege(p); reg_t npc; |