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author | Andrew Waterman <andrew@sifive.com> | 2024-09-02 23:38:13 -0500 |
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committer | GitHub <noreply@github.com> | 2024-09-02 23:38:13 -0500 |
commit | cb78f095ded11a980ea3b2609676b87c9339cb41 (patch) | |
tree | 20cbcf6f2ae7dee15594d699e4a0c3785d3b086e /riscv/devices.cc | |
parent | 2538c1fb203056fcdb96ea0f06dc1fbde5da73a5 (diff) | |
parent | 6a1a5db16b60abaecd235f78f5d70716bf47c9a9 (diff) | |
download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 |
vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions
Diffstat (limited to 'riscv/devices.cc')
0 files changed, 0 insertions, 0 deletions