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author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 14:57:10 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
commit | dc9a8e28eebefe693e0cd6baf60b933d7a973a3b (patch) | |
tree | 81b5bd51af9bfb7c7ff4f30a49e05e3b6b77dff8 /riscv/decode.h | |
parent | 3447aecd16e8ce34109a122d3f95b5e69176505f (diff) | |
download | riscv-isa-sim-dc9a8e28eebefe693e0cd6baf60b933d7a973a3b.zip riscv-isa-sim-dc9a8e28eebefe693e0cd6baf60b933d7a973a3b.tar.gz riscv-isa-sim-dc9a8e28eebefe693e0cd6baf60b933d7a973a3b.tar.bz2 |
Fix ignored-qualifiers warnings in get_field/set_field macros
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1b55502..2bf9ddf 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -19,6 +19,7 @@ #include "p_ext_macros.h" #include "v_ext_macros.h" #include <cinttypes> +#include <type_traits> typedef int64_t sreg_t; typedef uint64_t reg_t; @@ -282,8 +283,11 @@ do { \ if (rm > 4) throw trap_illegal_instruction(insn.bits()); \ rm; }) -#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) -#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) +#define get_field(reg, mask) \ + (((reg) & (std::remove_cv<decltype(reg)>::type)(mask)) / ((mask) & ~((mask) << 1))) + +#define set_field(reg, mask, val) \ + (((reg) & ~(std::remove_cv<decltype(reg)>::type)(mask)) | (((std::remove_cv<decltype(reg)>::type)(val) * ((mask) & ~((mask) << 1))) & (std::remove_cv<decltype(reg)>::type)(mask))) #define require_privilege(p) require(STATE.prv >= (p)) #define require_novirt() if (unlikely(STATE.v)) throw trap_virtual_instruction(insn.bits()) |