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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-16 10:42:08 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 14:12:53 +0800 |
| commit | 04154f2b305c222674c8cecf692b1b63edc8c6cb (patch) | |
| tree | 4fbda5e7782df92304b5ffc35c44ef64bb93731e /riscv/decode.h | |
| parent | 72df59bec2b2eaa3438a41b33df608571048d6ed (diff) | |
| download | riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.zip riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.gz riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.bz2 | |
Update fields name for sreg1/sreg2
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d27f682..a55b069 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -121,8 +121,8 @@ public: uint64_t rvc_lbimm() { return (x(5, 1) << 1) + x(6, 1); } uint64_t rvc_lhimm() { return (x(5, 1) << 1); } - uint64_t rvc_sreg1() { return x(7, 3); } - uint64_t rvc_sreg2() { return x(2, 3); } + uint64_t rvc_r1sc() { return x(7, 3); } + uint64_t rvc_r2sc() { return x(2, 3); } uint64_t rvc_rlist() { return x(4, 4); } uint64_t rvc_spimm() { return x(2, 2) << 4; } |