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author | Tim Newsome <tim@sifive.com> | 2018-02-01 14:32:00 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2018-02-01 14:32:00 -0800 |
commit | b2672e5d5271b346a71ec33ab42c88437b9b60d1 (patch) | |
tree | 33b6e163c6e3d5c45bdbacb0fbda86f3a7b51abc /riscv/debug_module.h | |
parent | d3d3681f3468c633bc93a727a35bc07348245440 (diff) | |
download | riscv-isa-sim-b2672e5d5271b346a71ec33ab42c88437b9b60d1.zip riscv-isa-sim-b2672e5d5271b346a71ec33ab42c88437b9b60d1.tar.gz riscv-isa-sim-b2672e5d5271b346a71ec33ab42c88437b9b60d1.tar.bz2 |
Add --debug-sba option
This lets the user control whether the system bus access implements bus
mastering.
Diffstat (limited to 'riscv/debug_module.h')
-rw-r--r-- | riscv/debug_module.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/debug_module.h b/riscv/debug_module.h index d581be8..36037b4 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -74,7 +74,7 @@ typedef struct { class debug_module_t : public abstract_device_t { public: - debug_module_t(sim_t *sim, unsigned progbufsize); + debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits); ~debug_module_t(); void add_device(bus_t *bus); @@ -96,6 +96,7 @@ class debug_module_t : public abstract_device_t // Actual size of the program buffer, which is 1 word bigger than we let on // to implement the implicit ebreak at the end. unsigned program_buffer_bytes; + unsigned max_bus_master_bits ; static const unsigned debug_data_start = 0x380; unsigned debug_progbuf_start; |