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| author | YenHaoChen <howard25336284@gmail.com> | 2023-07-17 12:27:59 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-25 08:41:17 +0800 |
| commit | e7e188011182a60c94bf2b35c94f02795d906da4 (patch) | |
| tree | 6771c1375002a61bde53f11e5cf039e49eedef4c /riscv/csrs.cc | |
| parent | 7f22022e1ad4019afb18e48ceb76ec9e6f483b50 (diff) | |
| download | riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.zip riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.tar.gz riscv-isa-sim-e7e188011182a60c94bf2b35c94f02795d906da4.tar.bz2 | |
legalize henvcfg.CBIE
The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 65f5594..34c03a5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -916,7 +916,7 @@ bool envcfg_csr_t::unlogged_write(const reg_t val) noexcept { // implement class henvcfg_csr_t henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg): - masked_csr_t(proc, addr, mask, init), + envcfg_csr_t(proc, addr, mask, init), menvcfg(menvcfg) { } |