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author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 14:11:18 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 14:58:57 -0800 |
commit | 96be756b53c46e297fe8a2af916060013860f1bb (patch) | |
tree | 8449b84a265642ea0a6202e08a8714195a1d9a38 /riscv/csrs.cc | |
parent | e4126acfa47f7a7cb463a86782aa2dcef0796608 (diff) | |
download | riscv-isa-sim-96be756b53c46e297fe8a2af916060013860f1bb.zip riscv-isa-sim-96be756b53c46e297fe8a2af916060013860f1bb.tar.gz riscv-isa-sim-96be756b53c46e297fe8a2af916060013860f1bb.tar.bz2 |
Make misa.C read-only
This resolves the issue discussed in #1201.
Prior to 0adf9307, clearing misa.C would disable compressed instructions
and increase IALIGN to 32. Afterwards, clearing misa.C had essentially
no effect because Zca and friends would stay enabled. While AFAICS this
isn't technically incorrect, it certainly doesn't follow the principle
of least surprise.
Instead, remove the feature to toggle misa.C. The effect is that misa.C
is 1 iff C is included in the ISA string, and IALIGN is independent of
misa.C: specifically, IALIGN is 16 iff Zca is present.
(And of course C implies Zca.)
Removing the alignment check on misa writes is not a separate commit
because these two changes should be made atomically. Not checking
the alignment on misa writes goes hand-in-hand with misa.C being
read-only.
Diffstat (limited to 'riscv/csrs.cc')
-rw-r--r-- | riscv/csrs.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index d7d0a86..de9381c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -601,13 +601,12 @@ bool sstatus_csr_t::enabled(const reg_t which) { misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa): basic_csr_t(proc, addr, max_isa), max_isa(max_isa), - write_mask(max_isa & (0 // allow MAFDQCHV bits in MISA to be modified + write_mask(max_isa & (0 // allow MAFDQHV bits in MISA to be modified | (1L << ('M' - 'A')) | (1L << ('A' - 'A')) | (1L << ('F' - 'A')) | (1L << ('D' - 'A')) | (1L << ('Q' - 'A')) - | (1L << ('C' - 'A')) | (1L << ('H' - 'A')) | (1L << ('V' - 'A')) ) @@ -619,10 +618,6 @@ reg_t misa_csr_t::dependency(const reg_t val, const char feature, const char dep } bool misa_csr_t::unlogged_write(const reg_t val) noexcept { - // the write is ignored if increasing IALIGN would misalign the PC - if (!(val & (1L << ('C' - 'A'))) && (state->pc & 2)) - return false; - reg_t adjusted_val = val; adjusted_val = dependency(adjusted_val, 'D', 'F'); adjusted_val = dependency(adjusted_val, 'Q', 'D'); |