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| author | YenHaoChen <howard25336284@gmail.com> | 2022-11-23 08:55:49 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-05 21:41:11 +0800 |
| commit | 200ee39b7ab67cabb3484b8d20b1e167ed33628b (patch) | |
| tree | b9c6758971d4d85fb87d99ad2468a86f513137a3 /riscv/csrs.cc | |
| parent | af99d52f256edcf1c70941210a225eed6a60eb35 (diff) | |
| download | riscv-isa-sim-200ee39b7ab67cabb3484b8d20b1e167ed33628b.zip riscv-isa-sim-200ee39b7ab67cabb3484b8d20b1e167ed33628b.tar.gz riscv-isa-sim-200ee39b7ab67cabb3484b8d20b1e167ed33628b.tar.bz2 | |
clear mevent.VUINH and mevent.VSINH when misa.H is cleared
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index f543cb1..d3314ba 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -650,6 +650,10 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { state->mie->write_with_mask(MIP_HS_MASK, 0); // also takes care of hie, sie state->mip->write_with_mask(MIP_HS_MASK, 0); // also takes care of hip, sip, hvip state->hstatus->write(0); + for (reg_t i = 3; i < N_HPMCOUNTERS + 3; ++i) { + const reg_t new_mevent = state->mevent[i - 3]->read() & ~(MHPMEVENT_VUINH | MHPMEVENT_VSINH); + state->mevent[i - 3]->write(new_mevent); + } } return basic_csr_t::unlogged_write(new_misa); |