diff options
| author | Andrew Waterman <andrew@sifive.com> | 2023-02-05 15:35:11 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-02-06 15:07:08 -0800 |
| commit | 13f075e7af30425227cb1323980397d513de76a2 (patch) | |
| tree | 2a2adf005e9ef8897134eefae27833cb96735797 /riscv/csrs.cc | |
| parent | 431813d8e27788dd69090c9f6810d06b803891a6 (diff) | |
| download | riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.zip riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.tar.gz riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.tar.bz2 | |
Make JVT CSR definition account for dynamically disabling Zcmt
No functional change yet.
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index de9381c..678a738 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1509,6 +1509,9 @@ jvt_csr_t::jvt_csr_t(processor_t* const proc, const reg_t addr, const reg_t init void jvt_csr_t::verify_permissions(insn_t insn, bool write) const { basic_csr_t::verify_permissions(insn, write); + if (!proc->extension_enabled(EXT_ZCMT)) + throw trap_illegal_instruction(insn.bits()); + if (proc->extension_enabled(EXT_SMSTATEEN)) { if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & SSTATEEN0_JVT)) throw trap_illegal_instruction(insn.bits()); |