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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-19 21:04:41 -0800 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-20 14:53:58 -0800 |
| commit | 0f85dacdb5a0912ff4f782bb07bb733bd2e0d7ba (patch) | |
| tree | 1fd42f658ede36bdfa25ab3ae8dd56f51b68eb88 /riscv/csrs.cc | |
| parent | f8592e43ebf971f9df1ab7aa7f06d1bdebd8390e (diff) | |
| download | riscv-isa-sim-0f85dacdb5a0912ff4f782bb07bb733bd2e0d7ba.zip riscv-isa-sim-0f85dacdb5a0912ff4f782bb07bb733bd2e0d7ba.tar.gz riscv-isa-sim-0f85dacdb5a0912ff4f782bb07bb733bd2e0d7ba.tar.bz2 | |
Check commitlog-enable dynamicallly for csr_t::log_special_write
This incurs a negligible performance impact
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 48b3e56..d7d0a86 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1,6 +1,5 @@ // See LICENSE for license details. -#include "config.h" // For std::any_of #include <algorithm> @@ -62,9 +61,8 @@ void csr_t::log_write() const noexcept { } void csr_t::log_special_write(const reg_t UNUSED address, const reg_t UNUSED val) const noexcept { -#if defined(RISCV_ENABLE_COMMITLOG) - proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0}; -#endif + if (proc->get_log_commits_enabled()) + proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0}; } reg_t csr_t::written_value() const noexcept { |