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author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-13 16:26:11 -0800 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-15 14:02:39 -0800 |
commit | ebc936767735fcd152cf51e6223dc2294b658d92 (patch) | |
tree | 4a924e0165da54d1f1220caf0d277a0b443a2810 /riscv/cfg.cc | |
parent | d00c01d2af6c141c0a9147533323582e6491e9c3 (diff) | |
download | riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.zip riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.tar.gz riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.tar.bz2 |
Add cfg.cc to hold internal implementation of mem_cfg_t
Diffstat (limited to 'riscv/cfg.cc')
-rw-r--r-- | riscv/cfg.cc | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/riscv/cfg.cc b/riscv/cfg.cc new file mode 100644 index 0000000..ef1d579 --- /dev/null +++ b/riscv/cfg.cc @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#include "cfg.h" +#include "mmu.h" +#include "decode.h" + +mem_cfg_t::mem_cfg_t(reg_t base, reg_t size) : base(base), size(size) +{ + assert(mem_cfg_t::check_if_supported(base, size)); +} + +bool mem_cfg_t::check_if_supported(reg_t base, reg_t size) +{ + // The truth of these conditions should be ensured by whatever is creating + // the regions in the first place, but we have them here to make sure that + // we can't end up describing memory regions that don't make sense. They + // ask that the page size is a multiple of the minimum page size, that the + // page is aligned to the minimum page size, that the page is non-empty and + // that the top address is still representable in a reg_t. + return (size % PGSIZE == 0) && + (base % PGSIZE == 0) && + (base + size > base); +} |