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author | takeoverjp <takeoverjp@gmail.com> | 2018-09-25 06:02:48 +0900 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-09-24 14:02:48 -0700 |
commit | 0b8700bb6196f201c3519c944aa7f9ea881a55b8 (patch) | |
tree | 2f5ed81a845a30b1c3368a291319ff2f4a47489e /riscv/cachesim.h | |
parent | 6fecdb16d72b71734b35f494023f5edc8804327c (diff) | |
download | riscv-isa-sim-0b8700bb6196f201c3519c944aa7f9ea881a55b8.zip riscv-isa-sim-0b8700bb6196f201c3519c944aa7f9ea881a55b8.tar.gz riscv-isa-sim-0b8700bb6196f201c3519c944aa7f9ea881a55b8.tar.bz2 |
Add "--log-cache-miss" option to generate a log of cache miss. (#241)
* Add "--log-cache-miss" option to generate a log of cache miss.
- This option must be used with "--ic" and/or "--dc" options
to enable cache simulation.
- This option is useful with "-l" option to understand
which instruction has caused the cache miss.
* Modify log format of cache miss to reduce log size.
Diffstat (limited to 'riscv/cachesim.h')
-rw-r--r-- | riscv/cachesim.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h index d597f79..259725a 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -29,6 +29,7 @@ class cache_sim_t void access(uint64_t addr, size_t bytes, bool store); void print_stats(); void set_miss_handler(cache_sim_t* mh) { miss_handler = mh; } + void set_log(bool _log) { log = _log; } static cache_sim_t* construct(const char* config, const char* name); @@ -58,6 +59,7 @@ class cache_sim_t uint64_t writebacks; std::string name; + bool log; void init(); }; @@ -88,6 +90,10 @@ class cache_memtracer_t : public memtracer_t { cache->set_miss_handler(mh); } + void set_log(bool log) + { + cache->set_log(log); + } protected: cache_sim_t* cache; |