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author | Megan Wachs <megan@sifive.com> | 2020-02-10 09:37:40 -0800 |
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committer | Megan Wachs <megan@sifive.com> | 2020-02-10 09:37:40 -0800 |
commit | 6b90a455dc185d25a7cdd69b89d7b43cfbd43751 (patch) | |
tree | 8c797e00e0a855ad2c46b501fcfe88f49a6923a1 /fesvr | |
parent | 60698a4a66edd7011d054be27fa30efd7aabee3e (diff) | |
download | riscv-isa-sim-6b90a455dc185d25a7cdd69b89d7b43cfbd43751.zip riscv-isa-sim-6b90a455dc185d25a7cdd69b89d7b43cfbd43751.tar.gz riscv-isa-sim-6b90a455dc185d25a7cdd69b89d7b43cfbd43751.tar.bz2 |
FESVR: Can't read a DM register when DMACTIVE=0
Diffstat (limited to 'fesvr')
-rw-r--r-- | fesvr/dtm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 5409321..46032c3 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -137,7 +137,7 @@ void dtm_t::resume(int hartsel) current_hart = hartsel; if (running) { - write(DMI_DMCONTROL, 0); + write(DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); // Read dmstatus to avoid back-to-back writes to dmcontrol. read(DMI_DMSTATUS); } |