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| author | Andrew Waterman <andrew@sifive.com> | 2022-11-23 16:38:42 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-23 16:38:55 -0800 |
| commit | bbb068fc644e5557b38c6d3f3616345313f62715 (patch) | |
| tree | f05faf16a4b7d69d3b54622c386c1aecc637517a /disasm | |
| parent | 86595060b1dfd28384ff8cd21d0023808ba957a4 (diff) | |
| download | riscv-isa-sim-bbb068fc644e5557b38c6d3f3616345313f62715.zip riscv-isa-sim-bbb068fc644e5557b38c6d3f3616345313f62715.tar.gz riscv-isa-sim-bbb068fc644e5557b38c6d3f3616345313f62715.tar.bz2 | |
Enable Zcb by default in disassembler
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 9e8a4ec..0ec67bd 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2225,7 +2225,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gqchv_zfh_zba_zbb_zbc_zbs_zicbom_zicboz_zkn_zkr_zks_svinval_xbitmanip"; + "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zkn_zkr_zks_svinval_xbitmanip"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); |