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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-21 22:53:05 -0800 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-23 23:49:36 -0800 |
commit | 487f1b7cd8fc74e94ac76f8912ce8f3e335ba940 (patch) | |
tree | 38f53a31dd7c57684dfc38ed18291bd8079c7271 /disasm | |
parent | 15f84304187ca881f206cdf4e2dba9f706902013 (diff) | |
download | riscv-isa-sim-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.zip riscv-isa-sim-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.tar.gz riscv-isa-sim-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.tar.bz2 |
rvv: rename sqrt/reciprocal instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index b5c76dc..39ae041 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1240,8 +1240,8 @@ disassembler_t::disassembler_t(int xlen) //vfunary1 DISASM_INSN("vfsqrt.v", vfsqrt_v, 0, {&vd, &vs2, &opt, &vm}); - DISASM_INSN("vfrsqrte7.v", vfrsqrte7_v, 0, {&vd, &vs2, &opt, &vm}); - DISASM_INSN("vfrece7.v", vfrece7_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_INSN("vfrsqrt7.v", vfrsqrt7_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_INSN("vfrec7.v", vfrec7_v, 0, {&vd, &vs2, &opt, &vm}); DISASM_INSN("vfclass.v", vfclass_v, 0, {&vd, &vs2, &opt, &vm}); DISASM_OPIV_VF_INSN(vfmul); |