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| author | Ved Shanbhogue <ved@rivosinc.com> | 2023-09-23 11:17:48 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-10-18 08:52:02 -0700 |
| commit | 762ed3f5c849d1c7f7e9fff6da3712531663d7a8 (patch) | |
| tree | 2409875db1fe86c225e3e0d8e2f1267d4d55e371 /disasm/isa_parser.cc | |
| parent | 4eb1cceb3d7ddb73a695fd58ee7a819641de2522 (diff) | |
| download | riscv-isa-sim-762ed3f5c849d1c7f7e9fff6da3712531663d7a8.zip riscv-isa-sim-762ed3f5c849d1c7f7e9fff6da3712531663d7a8.tar.gz riscv-isa-sim-762ed3f5c849d1c7f7e9fff6da3712531663d7a8.tar.bz2 | |
add zcmop extension instructions
Diffstat (limited to 'disasm/isa_parser.cc')
| -rw-r--r-- | disasm/isa_parser.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index d5dc439..3291f7d 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -292,6 +292,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SSCSRIND] = true; } else if (ext_str == "smcntrpmf") { extension_table[EXT_SMCNTRPMF] = true; + } else if (ext_str == "zcmop") { + extension_table[EXT_ZCMOP] = true; } else if (ext_str[0] == 'x') { extension_table['X'] = true; if (ext_str.size() == 1) { |