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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-21 00:34:20 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-21 01:14:02 -0800 |
| commit | b5f68dc55c2b310d24db35a3c7df1ad86509ab61 (patch) | |
| tree | 05d37c008d7d15b4f0d4a1d1f09408ca3c0425b5 /config.h.in | |
| parent | 7831b3e5f22602f373d580dd36b87a8aa02d2436 (diff) | |
| download | riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.zip riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.tar.gz riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.tar.bz2 | |
Remove --enable-histogram option
It's now redundant.
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/config.h.in b/config.h.in index 461cb5d..c89b10d 100644 --- a/config.h.in +++ b/config.h.in @@ -105,9 +105,6 @@ /* Enable support for running target in either endianness */ #undef RISCV_ENABLE_DUAL_ENDIAN -/* Enable PC histogram generation */ -#undef RISCV_ENABLE_HISTOGRAM - /* Enable hardware support for misaligned loads and stores */ #undef RISCV_ENABLE_MISALIGNED |