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author | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:19:11 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:21:06 -0800 |
commit | fc572daaef35fdc081466e6a67413b1f3b4d6a3e (patch) | |
tree | 1b13e962055a28f0d3044720f2f6e2b05c3addfc /README.md | |
parent | 2fbc6cde0b6b0e7d4ef77ae092c4ae286a77e2bf (diff) | |
download | riscv-isa-sim-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.zip riscv-isa-sim-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.gz riscv-isa-sim-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.bz2 |
Support RV32E/RV64E base ISAs
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -10,6 +10,7 @@ completion of the US transcontinental railway. Spike supports the following RISC-V ISA features: - RV32I and RV64I base ISAs, v2.1 + - RV32E and RV64E base ISAs, v1.9 - Zifencei extension, v2.0 - Zicsr extension, v2.0 - M extension, v2.0 |