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author | YenHaoChen <howard25336284@gmail.com> | 2022-11-16 13:02:02 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 09:29:00 +0800 |
commit | 8da8a8c89a937eb4e97fa1158deda84721b5900a (patch) | |
tree | 5242801a0c837bc4b32fc8461c2197e284467a4f /README.md | |
parent | 8ffff21ac65199dfe56a95388f959e7ee7095561 (diff) | |
download | riscv-isa-sim-8da8a8c89a937eb4e97fa1158deda84721b5900a.zip riscv-isa-sim-8da8a8c89a937eb4e97fa1158deda84721b5900a.tar.gz riscv-isa-sim-8da8a8c89a937eb4e97fa1158deda84721b5900a.tar.bz2 |
triggers: add etrigger_t
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -38,7 +38,7 @@ Spike supports the following RISC-V ISA features: - Svpbmt extension, v1.0 - Svinval extension, v1.0 - Debug v0.14 - - 4 triggers support type=2 (mcontrol), type=4 (itrigger), and type=15 (disabled) + - 4 triggers support type=2 (mcontrol), type=4 (itrigger), type=5 (etrigger), and type=15 (disabled) - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 |