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author | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:40:14 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:40:14 -0800 |
commit | 425e858340459c9eb219e85a805b4d7011b42e46 (patch) | |
tree | 3f0604b0f22de47f154ae8d0c6e57a09e17cea01 /README.md | |
parent | 3e9d1627d21074c139a5c7b95ff792d885f87e6c (diff) | |
parent | 54fc10571d8de5bc26eeda98ee405b75cdc9eb75 (diff) | |
download | riscv-isa-sim-425e858340459c9eb219e85a805b4d7011b42e46.zip riscv-isa-sim-425e858340459c9eb219e85a805b4d7011b42e46.tar.gz riscv-isa-sim-425e858340459c9eb219e85a805b4d7011b42e46.tar.bz2 |
Merge branch 'plctlab-plct-zce-upstream'
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -42,6 +42,12 @@ Spike supports the following RISC-V ISA features: - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 + - Zca extension, v1.0 + - Zcb extension, v1.0 + - Zcf extension, v1.0 + - Zcd extension, v1.0 + - Zcmp extension, v1.0 + - Zcmt extension, v1.0 As a Spike extension, the remainder of the proposed [Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) |