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author | YenHaoChen <howard25336284@gmail.com> | 2022-11-16 15:45:01 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-30 12:11:42 +0800 |
commit | 414a9c11e48068304cda81380f1322fd4611c5f6 (patch) | |
tree | b1c01c63af197cc50fd9df582751f7d2b042cf1d /README.md | |
parent | b3ab18867eacbe28cb9c6435d065d01cc704b5d7 (diff) | |
download | riscv-isa-sim-414a9c11e48068304cda81380f1322fd4611c5f6.zip riscv-isa-sim-414a9c11e48068304cda81380f1322fd4611c5f6.tar.gz riscv-isa-sim-414a9c11e48068304cda81380f1322fd4611c5f6.tar.bz2 |
triggers: add disabled_trigger_t
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -38,7 +38,7 @@ Spike supports the following RISC-V ISA features: - Svpbmt extension, v1.0 - Svinval extension, v1.0 - Debug v0.14 - - 4 triggers fixed to type=2 (mcontrol) + - 4 triggers support type=2 (mcontrol) and type=15 (disabled) - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 |