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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:41:07 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:40:00 -0800 |
| commit | 07d5b086dd5c92896b4f602c16a7f55be7db5fd6 (patch) | |
| tree | 66d706b902926cca277984a01e9ac030bcfdb551 /README.md | |
| parent | 90a246790f9352715231c486e0ee325c82eba482 (diff) | |
| download | riscv-isa-sim-07d5b086dd5c92896b4f602c16a7f55be7db5fd6.zip riscv-isa-sim-07d5b086dd5c92896b4f602c16a7f55be7db5fd6.tar.gz riscv-isa-sim-07d5b086dd5c92896b4f602c16a7f55be7db5fd6.tar.bz2 | |
add Zc* to README.md
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -41,6 +41,12 @@ Spike supports the following RISC-V ISA features: - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 + - Zca extension, v1.0 + - Zcb extension, v1.0 + - Zcf extension, v1.0 + - Zcd extension, v1.0 + - Zcmp extension, v1.0 + - Zcmt extension, v1.0 As a Spike extension, the remainder of the proposed [Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) |