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| author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:40:20 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-30 11:33:06 +0800 |
| commit | 0531acb756acef2fb1f82f355e522a9ab0840926 (patch) | |
| tree | 14a556524aa2e917c627ab989c6577b6190464f3 /README.md | |
| parent | e566c454fa88bf770d66a88298deb6daf2d80031 (diff) | |
| download | riscv-isa-sim-0531acb756acef2fb1f82f355e522a9ab0840926.zip riscv-isa-sim-0531acb756acef2fb1f82f355e522a9ab0840926.tar.gz riscv-isa-sim-0531acb756acef2fb1f82f355e522a9ab0840926.tar.bz2 | |
update README
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -33,6 +33,7 @@ Spike supports the following RISC-V ISA features: - Svnapot extension, v1.0 - Svpbmt extension, v1.0 - Svinval extension, v1.0 + - CMO extension, v1.0 - Debug v0.14 As a Spike extension, the remainder of the proposed |