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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /README.md | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | riscv-isa-sim-plic_uart_v1.zip riscv-isa-sim-plic_uart_v1.tar.gz riscv-isa-sim-plic_uart_v1.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -27,6 +27,10 @@ Spike supports the following RISC-V ISA features: - Zbb extension, v1.0 - Zbc extension, v1.0 - Zbs extension, v1.0 + - Zfh and Zfhmin half-precision floating-point extensions, v1.0 + - Zfinx extension, v1.0 + - Zmmul integer multiplication extension, v1.0 + - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0 - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 - Hypervisor extension, v1.0 @@ -35,6 +39,9 @@ Spike supports the following RISC-V ISA features: - Svinval extension, v1.0 - CMO extension, v1.0 - Debug v0.14 + - Smepmp extension v1.0 + - Smstateen extension, v1.0 + - Sscofpmf v0.5.2 As a Spike extension, the remainder of the proposed [Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) |